1. Field of the Invention
The present invention is directed to a digital delay circuit wherein the amount of delay can be variably set by a digital value, and also to a digital PLL (phase lock loop) circuit for generating an internal clock which follows a phase of an external clock.
2. Background of the Invention
A conventional digital PLL circuit, as set forth, for example, in U.S. Pat. No. 5,422,835, uses a pulse produced by shifting a phase by a plurality of delay lines, to generate an output signal dividing a cycle of the external clock.
FIG. 11 is a circuit diagram showing a conventional digital PLL circuit 900 introduced by U.S. Pat. No. 5,422,835. With reference to this figure, variable delay lines 1 through 3 generate pulses PG13, PG23 and PG33 having phase differences of 120.degree., 240.degree., and 360.degree., respectively. Then, with a toggle latch from a logical sum of the pulses PG13, PG23 and PG33, an output signal dividing a cycle of an external clock signal EXTR into one and half is generated.
Thus, a total amount of delay of the variable delay lines 1 through 3 has to correspond to one cycle of the external clock. Further, each of the three delay lines includes delay portions of the same delay amount.
In this way, the conventional digital PLL circuit 900 requires the delay lines having the same delay amount with one cycle of the external clock. Thus, the number of delay portions increases as one cycle of the external clock becomes longer, which increases the size of the circuit. Moreover, variable potential at each node in the delay lines increases power consumption in the digital PLL circuit.